1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a burst transfer memory.
2. Description of the Related Art
An increase in speed of a semiconductor memory device (hereinafter referred to as a “memory”) conventionally tends to result in an increase in chip size of the memory. For example, to implement a memory with a large storage capacity and a small chip size, it is desirable to increase the number of rows and columns in a cell array as much as possible. On the other hand, to implement a high-speed memory, the speed is increased by reducing the number of rows and columns in the cell array according to requirements to reduce loads on bit and word lines. Thus, in this case, the chip size of the entire memory tends to increase.
Now, this problem will be described in further detail with reference to FIGS. 1A, 1B, 2A, and 2B. A memory 101, shown in FIG. 1A, is composed of a cell array 103 consisting of 100 rows and 100 columns, a peripheral circuit 104, word lines WL, and bit lines BL. Further, a memory 102, shown in FIG. 1B, is composed of, for example, 100 cell arrays (hereinafter referred to as “sub-arrays”) consisting of ten cell arrays arranged in both row and column directions and each of which consists of 10 rows and 10 columns, a peripheral circuit 106, word lines WL, and bit lines BL.
To increase the speed of the memory 101, shown in FIG. 1A, the cell array 103 may be divided into a large number of sub-arrays 105 as shown in FIG. 1B to reduce loads on the word lines WL. However, if the cell array is divided into a large number of sub-arrays, the sum of occupation areas of the peripheral circuit 106, shown in FIG. 1B, increases drastically compared to the occupation areas of the peripheral circuit 104, shown in FIG. 1A. Accordingly, with the same memory capacity, the chip area of the memory 102 increases sharply above that of the memory 101.
On the other hand, as a memory that operate at a higher speed in spite of its large cell array matrix, a page access memory is known wherein a row address is used to select a word line so that memory data connected to the word line can be accessed by consecutively accessing column addresses and then input or output at a high speed. In this manner, the time required to access memory data can be drastically reduced compared to random access operations. However, with a memory with a large cell array matrix, when a top address of a page is accessed, much time is disadvantageously required to activate the corresponding word line.
Thus, there has hitherto been a tradeoff relationship between the access speed and cell array area of a memory. Consequently, it is difficult to reduce the area of a large-capacity memory while increasing the speed thereof.
That is, for a memory for which priority is given to a larger memory capacity, it is possible to minimize the area of the entire memory by increasing the number of rows and columns in the cell array as shown at 101 in FIG. 1A. However, if an attempt is made to increase the speed by reducing the number of rows and columns in the cell array to reduce loads on the bit and word lines as shown at 102 in FIG. 1B, then the area of the entire memory increases relative to the same memory capacity.
Further, for a page access memory, if priority is given to page accesses faster than the first (top address) random access as shown at 101 in FIG. 2A, then it is possible to increase the size of the cell array matrix, while minimizing the chip area. However, if it is desirable to increase not only the speed of page accesses but also the speed of the first random access as shown at 102 in FIG. 2B, then the chip area disadvantageously increases because the cell array must be divided into smaller cell array matrices in order to increase the speed of random accesses.
As described above, for the conventional large capacity memories, there is a tradeoff relationship between the access speed and cell array area of the memory, thereby making it difficult to reduce the chip area of the large capacity memory, while achieving high-speed operations. The embodiments of the present invention are provided to solve these problems. It is an aspect of the present invention to provide a large capacity memory which has a reduced chip area and which can operate at high speeds.